Hardware and runtime coordinated load balancing for parallel applications
US9619290B2 · kind B2 · utility
3Cited by
3References
20Claims
0Family size
Assignee
Inventors
Key dates
| Filing date | Mar 6, 2015 |
| Grant date | Apr 11, 2017 |
| Priority date | — |
| Expiry date | Mar 6, 2035 |
Classification
- Technology area (CPC Y)Emerging Cross-Sectional Technologies
- CPC primaryY02D10/00
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
A method of balancing execution rates for a plurality of parallel program loops being executed concurrently by a processor may include estimating a completion time for each program loop of the plurality of program loops, determining a difference between the estimated completion time of a first program loop of the plurality of program loops and the estimated completion time of a second program loop of the plurality of program loops, and decreasing the difference by adjusting an execution rate of the first program loop.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.