Patent · US Active

Memory circuits, method for accessing a memory and method for repairing a memory

US9619318B2 · kind B2 · utility

2Cited by

5References

10Claims

0Family size

Assignee

Intel Deutschland GmbH · DE

Inventors

Andreas Leininger · Birkenfeld, DE
Michael Richter · Ottobrunn, DE
Stefan Franz · Munich, DE

Key dates

Filing date	Feb 22, 2013
Grant date	Apr 11, 2017
Priority date	—
Expiry date	Mar 3, 2033

Classification

Technology area (CPC H)Electricity
CPC primaryH03M13/152
WIPO fieldComputer technology
WIPO sectorElectrical engineering

Abstract

A memory circuit is described comprising a plurality of memory elements, wherein each memory element is configured to store one data element of a plurality of data elements, an error correction information memory configured to store joint error correction information of the plurality of data elements, for each memory element, an error detection information memory storing error detection information for the data element stored in the memory element and a memory access circuit configured to, for an access to a memory element of the plurality of memory elements, check whether the error detection information for the data element stored in the memory element indicates an error of the data element stored in the memory element and, depending on whether the error detection information for the data element stored in the memory element indicates an error of the data element stored in the memory element, to process the error correction information for the access.

Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.