Flash memory system and operating method thereof
US9619327B2 · kind B2 · utility
Assignees
Inventors
Key dates
| Filing date | Nov 19, 2015 |
| Grant date | Apr 11, 2017 |
| Priority date | — |
| Expiry date | Nov 19, 2035 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH03M13/152
- WIPO fieldBasic communication processes
- WIPO sectorElectrical engineering
Abstract
An operation method of a flash memory system includes: obtaining first syndrome values to a codeword; obtaining locations of errors and the number of the locations of errors based on the first syndrome values; error-correcting the codeword by flipping bit values of error bits of the codeword based on the locations of errors to generate an error-corrected codeword; obtaining second syndrome values to the error-corrected codeword; determining whether an error is found in the error-corrected codeword based on the second syndrome values; changing the first syndrome values when it is determined that no error is found in the error-corrected codeword; and restoring the error-corrected codeword to the codeword by re-flipping the flipped bit values when it is determined that an error is found in the error-corrected codeword.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.