Patent · US Active

Single thread cache miss rate estimation

US9619385B2 · kind B2 · utility

3Cited by

7References

13Claims

0Family size

Assignee

International Business Machines Corporation · US

Inventors

James J. Bonanno · Wappingers Falls, US
Alper Buyuktosunoglu · White Plains, US
Brian W. Curran · Saugerties, US
Willm Hinrichs · Holzgerlingen, DE
Christian Jacobi · West Park, US
Brian R. Prasky · Campbell Hall, US
Martin Recktenwald · Eppelheim, DE
Anthony Saporito · Highland, US
Vijayalakshmi Srinivasan · New York, US
John-David Wellman · Hopewell Junction, US

Key dates

Filing date	Feb 25, 2015
Grant date	Apr 11, 2017
Priority date	—
Expiry date	Oct 8, 2035

Classification

Technology area (CPC G)Physics
CPC primaryG06F2212/684
WIPO fieldComputer technology
WIPO sectorElectrical engineering

Abstract

Cache miss rates for threads operating in a simultaneous multi-threading computer processing environment can be estimated. The single thread rates can be estimated by monitoring a shared directory for cache misses for a first thread. Memory access requests can be routed to metering cache directories associated with the particular thread. Single thread misses to the shared directory and single thread misses to the associated metering cache directory are monitored and a performance indication is determined by comparing the cache misses with the thread misses. The directory in the associated metering cache is rotated, and a second sharing performance indication is determined.

Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.