Pulse mechanism for memory circuit interruption
US9620182B2 · kind B2 · utility
5Cited by
14References
27Claims
0Family size
Assignee
Inventors
Key dates
| Filing date | Dec 31, 2013 |
| Grant date | Apr 11, 2017 |
| Priority date | — |
| Expiry date | Aug 26, 2035 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG11C16/32
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
In a memory system where multiple memory chips communicate their ready/busy status on a shared bus line, a pulse mechanism is used for the individual memory chips to indicate their ready/busy status to the controller. In one example, the controller assigns pulse durations of differing lengths to the memory dies to allow the controller to distinguish between them. Techniques for dealing with bus collisions between the pulses of different chips are also described.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.