Retention voltages for integrated circuits
US9620200B1 · kind B1 · utility
Assignee
Inventors
Key dates
| Filing date | Mar 26, 2016 |
| Grant date | Apr 11, 2017 |
| Priority date | — |
| Expiry date | Mar 26, 2036 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH10B10/12
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
Various implementations described herein may be directed to retention voltages for integrated circuits. In one implementation, an integrated circuit may include functional circuitry to store data bits, and may also include retention mode circuitry coupled to the functional circuitry to provide retention voltages to the functional circuitry, where the retention mode circuitry may include a first circuitry to provide a first retention voltage to the functional circuitry. The first circuitry may include a first diode device, and may include a first transistor device, a second diode device, or combinations thereof. The retention mode circuitry may also include a second circuitry to provide a second retention voltage to the functional circuitry, where the second circuitry includes second transistor devices. Further, the functional circuitry may be held in a data retention mode when the first retention voltage or the second retention voltage is provided to the functional circuitry.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.