Semiconductor memory device with selectively located air gaps
US9620451B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Apr 6, 2016 |
| Grant date | Apr 11, 2017 |
| Priority date | — |
| Expiry date | Apr 6, 2036 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH10B12/50
- WIPO fieldSemiconductors
- WIPO sectorElectrical engineering
Abstract
A method includes: forming a first contact hole by etching a first inter-layer dielectric layer; forming a preliminary first conductive plug that fills the first contact hole; forming a bit line structure over the preliminary first conductive plug; forming a first conductive plug by etching the preliminary first conductive plug so that a gap is formed between a sidewall of the first contact hole and the first conductive plug; forming an insulating plug in the gap; forming a multi-layer spacer including a sacrificial spacer; forming a second conductive plug neighboring the bit line structures and the first conductive plugs with the multi-layer spacer and the insulating plug therebetween; and forming a line-type air gap within the multi-layer spacer by removing the sacrificial spacer.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.