Middle-of-line (MOL) manufactured integrated circuits (ICs) employing local interconnects of metal lines using an elongated via, and related methods
US9620454B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Sep 12, 2014 |
| Grant date | Apr 11, 2017 |
| Priority date | — |
| Expiry date | Sep 12, 2034 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH01L2924/0002
- WIPO fieldSemiconductors
- WIPO sectorElectrical engineering
Abstract
Middle-of-line (MOL) manufactured integrated circuits (ICs) employing local interconnects of metal lines using an elongated via are disclosed. Related methods are also disclosed. In particular, different metal lines in a metal layer may need to be electrically interconnected during a MOL process for an IC. In this regard, to allow for metal lines to be interconnected without providing such interconnections above the metal lines that may be difficult to provide in a printing process for example, in an exemplary aspect, an elongated or expanded via(s) is provided in a MOL layer in an IC. The elongated via is provided in the MOL layer below the metal layer in the MOL layer and extended across two or more adjacent metal layers in the metal layer of the MOL layer. Moving the interconnections above the MOL layer can simplify the manufacturing of ICs, particularly at low nanometer (nm) node sizes.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.