Semiconductor arrangement, method for producing a semiconductor module, method for producing a semiconductor arrangement and method for operating a semiconductor arrangement

US9620459B2 · kind B2 · utility

Assignee

• Infineon Technologies AG · DE

Inventors

• Gottfried Beer · Nittendorf, DE
• Irmgard Escher-Poeppel · Regensburg, DE
• Juergen Hoegerl · Regensburg, DE
• Olaf Hohlfeld · Warstein, DE
• Peter Kanschat · Soest, DE

Key dates

• Filing date: Sep 3, 2014
• Grant date: Apr 11, 2017
• Expiry date: Sep 3, 2034

Classification

• Technology area (CPC H): Electricity
• CPC primary: H01L2924/35
• WIPO field: Semiconductors
• WIPO sector: Electrical engineering

Abstract

A semiconductor arrangement includes upper and lower contact plates and basic chip assemblies. Each chip assembly has a semiconductor chip having a semiconductor body with upper and lower spaced apart sides. An individual upper main electrode and an individual control electrode are arranged on the upper side. The chip assemblies have either respectively a separate lower main electrode arranged on the lower side of the semiconductor chip of the corresponding basic chip assembly, or a common lower main electrode, which for each of the chip assemblies is arranged on the lower side of the semiconductor body of that chip assembly. An electrical current between the individual upper main electrode and the individual or common lower main electrode is controllable by its control electrode. The chip assemblies are connected to one another with a material bonded connection by a dielectric embedding compound, forming a solid assembly.