Method of manufacturing semiconductor device
US9620522B1 · kind B1 · utility
Assignee
Inventor
Key dates
| Filing date | Feb 24, 2016 |
| Grant date | Apr 11, 2017 |
| Priority date | — |
| Expiry date | Feb 24, 2036 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH10D64/037
Abstract
The present disclosure provides a method of manufacturing a three dimensional memory device to suppress warpage of conductive patterns. The method may include providing a multilayered structure in which different material layers are alternately stacked over a substrate, etching partially the material layers to form a multi-step structure, each step being formed of at least one pair of the material layers, forming vertical support layers, each support layer being disposed on a top face of each step, removing partially the material layers to form recesses, filling the recesses with a conductive material to form gate lines, the gate line defining an upper portion of the step, and forming vertical contact plugs respectively on the upper portion of the step.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.