Memory device, memory cell and memory cell layout
US9620594B2 · kind B2 · utility
6Cited by
3References
20Claims
0Family size
Assignee
Inventors
Key dates
| Filing date | Sep 29, 2014 |
| Grant date | Apr 11, 2017 |
| Priority date | — |
| Expiry date | Sep 29, 2034 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH10D1/66
- WIPO fieldSemiconductors
- WIPO sectorElectrical engineering
Abstract
A memory device includes at least one memory cell. The memory cell includes first and second transistors, and first and second capacitors. The first transistor is coupled to a source line. The second transistor is coupled to the first transistor and a bit line. The first capacitor is coupled to a word line and the second transistor. The second capacitor is coupled to the second transistor and an erase gate.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.