IT instruction pre-decode
US9626185B2 · kind B2 · utility
1Cited by
4References
20Claims
0Family size
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Key dates
| Filing date | Feb 22, 2013 |
| Grant date | Apr 18, 2017 |
| Priority date | — |
| Expiry date | Mar 26, 2035 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG06F9/3844
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
Various techniques for processing and pre-decoding branches within an IT instruction block. Instructions are fetched and cached in an instruction cache, and pre-decode bits are generated to indicate the presence of an IT instruction and the likely boundaries of the IT instruction block. If an unconditional branch is detected within the likely boundaries of an IT instruction block, the unconditional branch is treated as if it were a conditional branch. The unconditional branch is sent to the branch direction predictor and the predictor generates a branch direction prediction for the unconditional branch.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.