Sense amplifier circuit with offset compensation for a non-volatile memory device
US9627011B1 · kind B1 · utility
Assignees
Inventors
Key dates
| Filing date | Jul 16, 2016 |
| Grant date | Apr 18, 2017 |
| Priority date | — |
| Expiry date | Jul 16, 2036 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH03F2203/45212
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
A method for operating a non-volatile memory device uses a sense amplifier that includes a first branch and a second branch. During a pre-charging step, a bit line of a memory array of the non-volatile memory device is biased in order to pre-charge the bit line. During the pre-charging step, an offset between the first branch and the second branch is detected and stored. During a reading step subsequent to the pre-charging step, a cell current is received from the bit line at the first branch and a reference current is received from a current-reference structure at the second branch. During the reading step, and amplified voltage is generated as a function of the cell current and the reference current. During the reading step, an output voltage is generated based on the amplified voltage compensated by the offset stored during the pre-charging step.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.