Semiconductor memory device and semiconductor system
US9627075B1 · kind B1 · utility
2Cited by
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18Claims
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Key dates
| Filing date | May 5, 2016 |
| Grant date | Apr 18, 2017 |
| Priority date | — |
| Expiry date | May 5, 2036 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG11C16/0483
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
A semiconductor memory device may include: a memory cell array comprising a plurality of memory cells coupled to a plurality of bit line pairs and a plurality of word lines; and an operation circuit suitable for setting a parameter corresponding to an input command, and performing an operation corresponding to the input command on the memory cell array based on the set parameter, wherein, when the input command is of the same type as a previous input command, the operation circuit skips setting the parameter for each of preset word line groups.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.