Insulated gate type semiconductor device
US9627248B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Feb 5, 2015 |
| Grant date | Apr 18, 2017 |
| Priority date | — |
| Expiry date | Feb 5, 2035 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH10D64/513
- WIPO fieldSemiconductors
- WIPO sectorElectrical engineering
Abstract
An insulating gate type semiconductor device being capable of easily depleting an outer periphery region is provided. The insulating gate type semiconductor device includes: first to fourth outer periphery trenches formed in a front surface of a semiconductor substrate; insulating layers located in the outer periphery trenches; fifth semiconductor regions being of a second conductive type and formed in ranges exposed to bottom surfaces of the outer periphery trenches; and a connection region connecting the fifth semiconductor region exposed to the bottom surface of the second outer periphery trench to the fifth semiconductor region exposed to the bottom surface of the third outer periphery trench. A clearance between the second and third outer periphery trenches is wider than each of a clearance between the first and second outer periphery trenches and a clearance between the third and fourth outer periphery trenches.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.