Package structure
US9627286B1 · kind B1 · utility
0Cited by
2References
15Claims
0Family size
Assignee
Inventors
Key dates
| Filing date | Jul 6, 2016 |
| Grant date | Apr 18, 2017 |
| Priority date | — |
| Expiry date | Jul 6, 2036 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH01L23/10
- WIPO fieldSemiconductors
- WIPO sectorElectrical engineering
Abstract
The invention provides a package structure which includes a substrate, at least one chip module, and a housing. The at least one chip module is located on the substrate. The housing includes an upper cover, a surrounding wall, and at least one adhesion enhancement structure. The surrounding wall is connected to the upper cover and encompasses the at least one chip module. The surrounding wall and the adhesion enhancement structure are bonded to the substrate by an adhesive. The adhesion enhancement structure includes an encircled hole or a semi-encircled hole.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.