Field effect transistor devices having interconnect structures and manufacturing method thereof
US9627316B1 · kind B1 · utility
10Cited by
0References
20Claims
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Key dates
| Filing date | Dec 15, 2015 |
| Grant date | Apr 18, 2017 |
| Priority date | — |
| Expiry date | Dec 15, 2035 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH01L2221/1063
- WIPO fieldSemiconductors
- WIPO sectorElectrical engineering
Abstract
A field effect transistor comprising a substrate, at least one gate stack structure, source and drain regions and an interconnect structure is described. The interconnect structure comprises a metal interconnect connected to a conductive region, an adhesion sheath structure and a cap layer. The adhesion sheath structure is disposed between the metal interconnect and inter-dielectric layers and surrounds the metal interconnect. The cap layer is disposed on the metal interconnect and covers a gap between the metal interconnect and the inter-dielectric layer.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.