Patent · US Active

Method to improve floating gate uniformity for non-volatile memory devices

US9627392B2 · kind B2 · utility

4Cited by

1References

20Claims

0Family size

Assignee

TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY LTD. · TW

Inventors

Harry-Hak-Lay Chuang · Austin, US
Chin-Yi Huang · Fremont, US
Ya-Chen Kao · Taoyuan, TW

Key dates

Filing date	Jan 30, 2015
Grant date	Apr 18, 2017
Priority date	—
Expiry date	Jan 30, 2035

Classification

Technology area (CPC H)Electricity
CPC primaryH01L21/3212
WIPO fieldSemiconductors
WIPO sectorElectrical engineering

Abstract

The present disclosure relates an integrated circuit (IC) for an embedded flash memory device. In some embodiments, the IC includes a memory array region and a boundary region surrounding the memory array region disposed over a semiconductor substrate. A hard mask is disposed at the memory array region comprising a plurality of discrete portions. The hard mask is disposed under a control dielectric layer of the memory array region.

Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.