Semiconductor device
US9627486B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Mar 18, 2013 |
| Grant date | Apr 18, 2017 |
| Priority date | — |
| Expiry date | Mar 18, 2033 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH10D64/252
Abstract
In an active region, p+ regions are selectively disposed in a surface layer of an n− drift layer on an n+ semiconductor substrate. A p-base layer is disposed on surfaces of the n− drift layer and the P+ regions, and an MOS structure is disposed on the p-base layer. In another portion of the active region, a p+ region is disposed to be in contact with the source electrode on the p+ regions. In a breakdown voltage structure region (100), a JTE structure having at least a P− region is disposed separately from the P+ regions and the p-base layer, to surround the active region. The P− region is electrically in contact with the P+ region in a portion in which the MOS structure is not formed, in the vicinity of the boundary between the active region and the breakdown voltage structure region.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.