Apparatus for a monotonic delay line, method for fast locking of a digital DLL with clock stop/start tolerance, apparatus and method for robust clock edge placement, and apparatus and method for clock offset tuning
US9628092B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Aug 31, 2015 |
| Grant date | Apr 18, 2017 |
| Priority date | — |
| Expiry date | Aug 31, 2035 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH03L7/0814
- WIPO fieldBasic communication processes
- WIPO sectorElectrical engineering
Abstract
Described is an apparatus comprising: a delay line including at least four delay stages coupled together in a series; a first multiplexer having a first input coupled to an output of a first delay stage of the at least four delay stages, and a second input coupled to an output of a third delay stage of the at least four delay stages; a second multiplexer having a first input coupled to an output of a second delay stage of the at least four delay stages, and a second input coupled to an output of a fourth delay stage of the at least four delay stages; and a phase interpolator coupled to outputs of the first and second multiplexers, the phase interpolator having an output.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.