Semiconductor memory devices including error correction circuits and methods of operating the semiconductor memory devices
US9632856B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Jan 11, 2016 |
| Grant date | Apr 25, 2017 |
| Priority date | — |
| Expiry date | Jan 11, 2036 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG11C29/783
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
A memory controller includes a controller input/output circuit configured to output a first command to read first data, and output a second command to read an error corrected portion of the first data. A memory device includes: an error detector, a data storage circuit and an error correction circuit. The error detector is configured to detect a number of error bits in data read from a memory cell in response to a first command. The data storage circuit is configured to store the read data if the detected number of error bits is greater than or equal to a first threshold value. The error correction circuit is configured to correct the stored data.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.