Apparatus for error simulation and method thereof
US9632894B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Apr 2, 2015 |
| Grant date | Apr 25, 2017 |
| Priority date | — |
| Expiry date | Aug 19, 2035 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG06F11/2215
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
The present invention relates to an apparatus for computing an error rate comprising: a first circuit interface being connected to a first sub-circuit receiving data and computing output data through a predetermined computation process; a second circuit interface and being connected to a first test circuit receiving the same data, which is inputted to the first sub-circuit, and computing output data through the predetermined computation process; an error injecting part injecting an error to the first test circuit; an error detecting part comparing output data of the first sub-circuit to output data of the first test circuit; and an error rate computing part computing input node error probability of the first sub-circuit by statistic processing of the compared result. The apparatus and method for computing error rate of the present invention is able to shorten the time required to obtain error probability, compared to the direct simulation of the full circuit.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.