Reorder buffer permitting parallel processing operations with repair on ordering hazard detection within interconnect circuitry
US9632955B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Feb 23, 2015 |
| Grant date | Apr 25, 2017 |
| Priority date | — |
| Expiry date | Oct 29, 2035 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG06F2212/621
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
A system-on-chip integrated circuit 2 includes interconnect circuitry 4 for communicating transactions between transaction sources and transaction destinations. A reorder buffer 26 serves to buffer and permit reordering of access transactions received from the transaction sources. Processing circuitry performs processing operations in parallel upon a given access transaction taken from the reorder buffer. Hazard detection and repair circuitry serves to detect an ordering hazard arising between the processing operations and if necessary cancel and repeat that processing operation. The access transactions and the reorder buffer are such that access transactions other than the access transaction for which a hazard has been detected may proceed independently of the necessity to cancel and repair that transaction thereby reducing the cost associated with cancelling and repair.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.