Multi-channel testing
US9633748B2 · kind B2 · utility
Assignee
Inventor
Key dates
| Filing date | Aug 17, 2015 |
| Grant date | Apr 25, 2017 |
| Priority date | — |
| Expiry date | Aug 17, 2035 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG11C2029/5602
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
Apparatus and methods can include an interface chip that can include a test channel to couple to a memory tester, a memory channel controller to couple with a plurality of memory arrays via a plurality of memory channels, and a test circuit coupled between the test channel and the channel controller, the test circuit to provide first and second test clock information to the memory channel controller. In certain examples, the test circuit can operate to receive multiple commands and to propagate the multiple commands to groups of memory channels substantially simultaneously in order to test cross-channel interference using the multi-channel memory. Additional apparatus and methods are disclosed.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.