Transistor fabrication technique including sacrificial protective layer for source/drain at contact location
US9633835B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Sep 6, 2013 |
| Grant date | Apr 25, 2017 |
| Priority date | — |
| Expiry date | Apr 3, 2034 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH10D64/017
- WIPO fieldSemiconductors
- WIPO sectorElectrical engineering
Abstract
Techniques are disclosed for transistor fabrication including a sacrificial protective layer for source/drain (S/D) regions to minimize contact resistance. The sacrificial protective layer may be selectively deposited on S/D regions after such regions have been formed, but prior to the deposition of an insulator layer on the S/D regions. Subsequently, after contact trench etch is performed, an additional etch process may be performed to remove the sacrificial protective layer and expose a clean S/D surface. Thus, the sacrificial protective layer can protect the contact locations of the S/D regions from contamination (e.g., oxidation or nitridation) caused by insulator layer deposition. The sacrificial protective layer can also protect the S/D regions from undesired insulator material remaining on the S/D contact surface, particularly for non-planar transistor structures (e.g., finned or nanowire/nanoribbon transistor structures).
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.