Semiconductor structure with resist protective oxide on isolation structure and method of manufacturing the same
US9633860B2 · kind B2 · utility
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19Claims
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Key dates
| Filing date | Jul 9, 2015 |
| Grant date | Apr 25, 2017 |
| Priority date | — |
| Expiry date | Jul 9, 2035 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH10D84/0135
- WIPO fieldSemiconductors
- WIPO sectorElectrical engineering
Abstract
A semiconductor structure includes an isolation structure, a gate stack, a spacer and a patterned resist protective oxide. The isolation structure is formed in a semiconductor substrate, and electrically isolates device regions of the semiconductor substrate. The gate stack is located on the isolation structure. The spacer is formed along a sidewall of the gate stack on the isolation structure. The patterned resist protective oxide is located on the isolation structure and covers a sidewall of the spacer such that the spacer is interposed between the patterned resist protective oxide and the gate stack.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.