Packages with interposers and methods for forming the same
US9633869B2 · kind B2 · utility
11Cited by
3References
20Claims
0Family size
Assignee
Inventors
Key dates
| Filing date | Aug 16, 2013 |
| Grant date | Apr 25, 2017 |
| Priority date | — |
| Expiry date | Sep 28, 2033 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH01L2924/3511
- WIPO fieldSemiconductors
- WIPO sectorElectrical engineering
Abstract
A package structure includes an interposer, a die over and bonded to the interposer, and a Printed Circuit Board (PCB) underlying and bonded to the interposer. The interposer is free from transistors therein (add transistor), and includes a semiconductor substrate, an interconnect structure over the semiconductor substrate, through-vias in the silicon substrate, and redistribution lines on a backside of the silicon substrate. The interconnect structure and the redistribution lines are electrically coupled through the through-vias.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.