Semiconductor device having vertical channel and air gap, and method of manufacturing thereof
US9634024B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Mar 9, 2015 |
| Grant date | Apr 25, 2017 |
| Priority date | — |
| Expiry date | Mar 9, 2035 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH10B43/35
Abstract
A semiconductor device is provided. Word lines are formed on a substrate. An air gap is interposed between two adjacent word lines. A channel structure penetrates through the word lines and the air gap. A memory cell is interposed between each word line and the channel structure. The memory cell includes a blocking pattern, a charge trap pattern and a tunneling insulating pattern. The blocking pattern conformally covers a top surface, a bottom surface, and a first side surface of each word line. The first side surface is adjacent to the channel structure. The charge trap pattern is interposed only between the first side surface and the channel structure.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.