Patent · US Active

Standard cell architecture for reduced leakage current and improved decoupling capacitance

US9634026B1 · kind B1 · utility

3Cited by

15References

12Claims

0Family size

Assignee

QUALCOMM Incorporated · US

Inventors

Satyanarayana Sahu · San Diego, US
Xiangdong Chen · Irvine, US
Ramaprasath Vilangudipitchai · San Diego, US
Dorav Kumar · San Diego, US

Key dates

Filing date	Jul 13, 2016
Grant date	Apr 25, 2017
Priority date	—
Expiry date	Jul 13, 2036

Classification

Technology area (CPC H)Electricity
CPC primaryH10D84/975
WIPO fieldBasic communication processes
WIPO sectorElectrical engineering

Abstract

A standard cell IC may include a plurality of pMOS transistors each including a pMOS transistor drain, a pMOS transistor source, and a pMOS transistor gate. Each pMOS transistor drain and pMOS transistor source of the plurality of pMOS transistors may be coupled to a first voltage source. The standard cell IC may also include a plurality of nMOS transistors each including an nMOS transistor drain, an nMOS transistor source, and an nMOS transistor gate. Each nMOS transistor drain and nMOS transistor source of the plurality of nMOS transistors are coupled to a second voltage source lower than the first voltage source.

Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.