Silicon and silicon germanium nanowire formation
US9634091B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Nov 2, 2015 |
| Grant date | Apr 25, 2017 |
| Priority date | — |
| Expiry date | Nov 2, 2035 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH10D30/0243
- WIPO fieldMicro-structural and nano-technology
- WIPO sectorChemistry
Abstract
Among other things, one or semiconductor arrangements, and techniques for forming such semiconductor arrangements are provided. For example, one or more silicon and silicon germanium stacks are utilized to form PMOS transistors comprising germanium nanowire channels and NMOS transistors comprising silicon nanowire channels. In an example, a first silicon and silicon germanium stack is oxidized to transform silicon to silicon oxide regions, which are removed to form germanium nanowire channels for PMOS transistors. In another example, silicon and germanium layers within a second silicon and silicon germanium stack are removed to form silicon nanowire channels for NMOS transistors. PMOS transistors having germanium nanowire channels and NMOS transistors having silicon nanowire channels are formed as part of a single fabrication process.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.