Power field effect transistor
US9634135B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Feb 27, 2013 |
| Grant date | Apr 25, 2017 |
| Priority date | — |
| Expiry date | Feb 27, 2033 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH10D64/62
Abstract
A field-effect transistors (FET) cell structure has a substrate, an epitaxial layer of a first conductivity type on the substrate, first and second base regions of the second conductivity type arranged within the epitaxial layer or well and spaced apart, and first and second source regions of a first conductivity type arranged within the first and second base region, respectively. Furthermore, a gate structure insulated from the epitaxial layer by an insulation layer is provided and arranged above the region between the first and second base regions and covering at least partly the first and second base region, and a drain contact reaches from a top of the device through the epitaxial layer to couple a top contact or metal layer with the substrate.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.