Thermal-aware compiler for parallel instruction execution in processors
US9639359B2 · kind B2 · utility
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18Claims
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Key dates
| Filing date | May 21, 2013 |
| Grant date | May 2, 2017 |
| Priority date | — |
| Expiry date | May 21, 2033 |
Classification
- Technology area (CPC Y)Emerging Cross-Sectional Technologies
- CPC primaryY02D10/00
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
Embodiments are described for a method for compiling instruction code for execution in a processor having a number of functional units by determining a thermal constraint of the processor, and defining instruction words comprising both real instructions and one or more no operation (NOP) instructions to be executed by the functional units within a single clock cycle, wherein a number of NOP instructions executed over a number of consecutive clock cycles is configured to prevent exceeding the thermal constraint during execution of the instruction code.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.