Parity protection of a register
US9639418B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Sep 1, 2015 |
| Grant date | May 2, 2017 |
| Priority date | — |
| Expiry date | Oct 21, 2035 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG06F11/102
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
The embodiments herein generate parity check data which serves as parity-on-parity. Stated differently, the parity check data can be used to determine if parity data stored in a memory element has been corrupted. For example, after generating the parity data, a computing system may set the parity check data depending on whether there is an even or odd number of logical ones (or logical zeros) in the parity data. Thus, when the parity data is read out of the memory element, if the parity data does not include the same number of even or odd bits, the parity check data indicates to the computing system that the parity data is corrupted. In one embodiment, to reduce the likelihood that the parity check data becomes corrupted, the computing system stores this data in hardened latches which are less susceptible to soft errors than other types of memory elements.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.