Ring protocol for low latency interconnect switch
US9639490B2 · kind B2 · utility
13Cited by
6References
19Claims
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Inventors
Key dates
| Filing date | Nov 29, 2011 |
| Grant date | May 2, 2017 |
| Priority date | — |
| Expiry date | Aug 20, 2032 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG06F30/367
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
Methods, systems, and apparatus for implementing low latency interconnect switches between CPU's and associated protocols. CPU's are configured to be installed on a main board including multiple CPU sockets linked in communication via CPU socket-to-socket interconnect links forming a CPU socket-to-socket ring interconnect. The CPU's are also configured to transfer data between one another by sending data via the CPU socket-to-socket interconnects. Data may be transferred using a packetized protocol, such as QPI, and the CPU's may also be configured to support coherent memory transactions across CPU's.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.