Method and apparatus for master-clone optimization during circuit analysis
US9639644B1 · kind B1 · utility
Assignee
Inventors
Key dates
| Filing date | Jan 27, 2015 |
| Grant date | May 2, 2017 |
| Priority date | — |
| Expiry date | Feb 2, 2035 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG06F30/39
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
A system, method and/or computer program for optimizing a circuit design. In some embodiments, a target block with an external boundary and external boundary pins is identified in an integrated circuit design. An area outside the target block is converted into a first macro, wherein the first macro has a physical library and a timing library and wherein the physical library has an internal boundary that corresponds to the external boundary of the target block and wherein the physical library has internal boundary pins that correspond to the external boundary pins of the target block. The target block is represented as a single block netlist and the block netlist is optimized with respect to the first macro. The steps may be repeated with respect to a master and clone(s) on the same integrated circuit enabling a single block netlist to be optimized for multiple instances of the same design IP.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.