Access methods and circuits for memory devices having multiple channels and multiple banks
US9640237B1 · kind B1 · utility
1Cited by
21References
20Claims
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Key dates
| Filing date | Sep 25, 2015 |
| Grant date | May 2, 2017 |
| Priority date | — |
| Expiry date | Sep 25, 2035 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG11C11/419
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
An integrated circuit (IC) device can include a plurality of banks, each including a plurality of memory cells, and separately accessible according to a received bank address value, each bank configured to enable accesses on different phases of an internal clock signal; and a plurality of channel groups, each channel group including a plurality of channels, each channel including its own data connections, address connections, and control input connections for accessing the banks, the channels of different groups accessing the memory banks on the different phases of the internal clock signal.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.