Multi-port memory cell
US9640251B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Aug 15, 2016 |
| Grant date | May 2, 2017 |
| Priority date | — |
| Expiry date | Aug 15, 2036 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG11C8/14
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
A circuit includes: a first word line; a second word line; and a memory cell. The memory cell includes: a first pass gate, between a transistor and a first data line (RBL), having a gate coupled to the first word line; the transistor having a drain coupled to the first pass gate, a source coupled to a reference node, and a gate coupled to a data node of the memory cell; and a second pass gate, between the data node and a second data line, having a gate coupled to the second word line. The first word line is configured to turn on the first pass gate. The second word line is configured to turn on the second pass gate after an elapse of a first delay.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.