Semiconductor device, structure and methods
US9640531B1 · kind B1 · utility
91Cited by
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20Claims
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Key dates
| Filing date | Jan 28, 2015 |
| Grant date | May 2, 2017 |
| Priority date | — |
| Expiry date | Jan 28, 2035 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH10D88/01
- WIPO fieldSemiconductors
- WIPO sectorElectrical engineering
Abstract
A 3D semiconductor device, including: a first layer including first transistors; a second layer overlaying the first layer, the second layer including second transistors, where the second layer includes at least one thru layer via with a diameter less than 200 nm, where the second layer includes an oscillator, and where the oscillator has a frequency stability of less than 100 ppm error/° C.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.