Vertical memory device with gate lines at the same level connected
US9640549B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Nov 6, 2014 |
| Grant date | May 2, 2017 |
| Priority date | — |
| Expiry date | Nov 6, 2034 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH10D30/693
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
A vertical memory device includes a substrate, a channel, gate lines and a connecting portion. A plurality of the channels extend in a first direction which is vertical to a top surface of a substrate. A plurality of the gate lines are stacked in the first direction to be spaced apart from each other and extend in a second, lengthwise direction, each gate line intersecting a set of channels and surrounding outer sidewalls of each channel of the set of channels. The gate lines forms a stepped structure which includes a plurality of vertical levels. A connecting portion connects a group of gate lines of the plurality of gate lines located at the same vertical level, the connecting portion diverging from the second direction in which the gate lines of the group of gate lines extend.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.