Semiconductor device having three-dimensional structure and method of manufacturing the same
US9640550B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Sep 13, 2016 |
| Grant date | May 2, 2017 |
| Priority date | — |
| Expiry date | Sep 13, 2036 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH10B43/50
- WIPO fieldSemiconductors
- WIPO sectorElectrical engineering
Abstract
A semiconductor device includes a semiconductor pattern; conductive layers each including a first portion through which the semiconductor pattern passes and a second portion having a thickness greater than the first portion, wherein the first portion of each conductive layer includes a first barrier pattern surrounding the semiconductor pattern and a material pattern, which is formed in the first barrier pattern and has an etch selectivity with respect to the first barrier pattern, and the second portion of each conductive layer includes a conductive pattern; and contact plugs connected to the second portion of each of the conductive layers.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.