Semiconductor device and method of forming a power MOSFET with interconnect structure to achieve lower RDSON
US9640638B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Jan 22, 2013 |
| Grant date | May 2, 2017 |
| Priority date | — |
| Expiry date | Jul 26, 2033 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH10D64/516
- WIPO fieldSemiconductors
- WIPO sectorElectrical engineering
Abstract
A semiconductor device has a substrate and gate structure over the substrate. A source region is formed in the substrate adjacent to the gate structure. A drain region in the substrate adjacent to the gate structure opposite the source region. An interconnect structure is formed over the substrate by forming a conductive plane electrically connected to the source region, and forming a conductive layer within openings of the conductive plane and electrically connected to the drain region. The interconnect structure can be formed as stacked conductive layers laid out in alternating strips. The conductive plane extends under a gate terminal of the semiconductor device. An insulating layer is formed over the substrate and a field plate is formed in the insulating layer. The field plate is electrically connected the source terminal. A stress relief layer is formed over a surface of the substrate opposite the gate structure.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.