Dual-loop programmable and dividerless clock generator for ultra low power applications
US9641183B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Oct 22, 2014 |
| Grant date | May 2, 2017 |
| Priority date | — |
| Expiry date | Oct 22, 2034 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH03L2207/50
- WIPO fieldBasic communication processes
- WIPO sectorElectrical engineering
Abstract
A programmable clock generator is provided which is particularly suitable for low power applications. The programmable clock generator is comprised of: an oscillator circuit that generates an output signal whose frequency is set by a control signal, two feedback loops for controlling output frequency and a loop select that selects which feedback loop is operational at a given time. In operation, the frequency loop operates to coarsely adjust the frequency of the output signal; whereas, the phase loop operates to finely adjust the frequency of the output signal. The clock generator is preferably implemented by transistors operating in or near the subthreshold region.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.