Input signal mismatch detection circuit
US9643558B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Feb 18, 2015 |
| Grant date | May 9, 2017 |
| Priority date | — |
| Expiry date | Jan 31, 2036 |
Classification
- Technology area (CPC B)Performing Operations; Transporting
- CPC primaryB60R2021/01286
- WIPO fieldTransport
- WIPO sectorMechanical engineering
Abstract
A system for detecting a mismatch between first and second input signals includes first and second analog-to-digital converters, a time-division multiplexing circuit, first and second processors, a time-division de-multiplexing circuit, and a gating circuit. The first processor includes a first sinc filter, a first trimmer, a first infinite impulse response (IIR) filter, and a first high pass filter (HPF). The second processor includes a second sinc filter, a second IIR filter, and a second HPF. A bandwidth of the second IIR filter and the second HPF is greater than a bandwidth of the first IIR filter and the first HPF. A transfer function of the first IIR filter and the first HPF uses floating-point coefficients and a transfer function of the second IIR filter and the second HPF uses coefficients that are an integral power of two.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.