Capacitance reduction for pillar structured devices
US9645262B2 · kind B2 · utility
Assignees
Inventors
Key dates
| Filing date | Nov 26, 2014 |
| Grant date | May 9, 2017 |
| Priority date | — |
| Expiry date | Nov 10, 2035 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH10F30/292
- WIPO fieldEnvironmental technology
- WIPO sectorChemistry
Abstract
In one embodiment, an apparatus includes: a first layer including a n+ dopant or p+ dopant; an intrinsic layer formed above the first layer, the intrinsic layer including a planar portion and pillars extending above the planar portion, cavity regions being defined between the pillars; and a second layer deposited on a periphery of the pillars thereby forming coated pillars, the second layer being substantially absent on the planar portion of the intrinsic layer between the coated pillars. The second layer includes an n+ dopant when the first layer includes a p+ dopant. The second layer includes a p+ dopant when the first layer includes an n+ dopant. The apparatus includes a neutron sensitive material deposited between the coated pillars and above the planar portion of the intrinsic layer. In additional embodiments, an upper portion of each of the pillars includes a same type of dopant as the second layer.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.