Adder decoder
US9645790B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Nov 11, 2014 |
| Grant date | May 9, 2017 |
| Priority date | — |
| Expiry date | Jun 30, 2035 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG06F7/50
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
The present disclosure relates to an add and decode hardware logic circuit for adding two n bit inputs, A and B. A series of n logic stages are each configured to perform a first operation of propagating a result of a preceding stage on the condition that the sum of A[m] and B[m] is equal to 0, wherein 0<=m<n, perform a second operation of performing a bitwise left shift by 2m of the result of the preceding stage on the condition that the sum of A[m] and B[m] is equal to 1, or perform a third operation of performing a bitwise left shift by 2m+1 of the result of the preceding stage on the condition that the sum of A[m] and B[m] is equal to 2. An output at the last stage provides a decoded sum of the inputs A and B.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.