Memory device and method of refreshing the same
US9646672B1 · kind B1 · utility
Assignee
Inventors
Key dates
| Filing date | Aug 15, 2016 |
| Grant date | May 9, 2017 |
| Priority date | — |
| Expiry date | Aug 15, 2036 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG11C2211/4068
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
A memory device includes a plurality of memory cells; a nonvolatile memory block suitable for simultaneously sensing one or more programmed weak addresses, and sequentially transmitting the sensed weak addresses; a weak address control block suitable for latching the weak addresses transmitted from the nonvolatile memory block, and outputting sequentially the latched weak addresses in a weak refresh operation; and a refresh control block suitable for controlling the memory cells corresponding to the counting address to be refreshed, in a normal refresh operation, and controlling the memory cells corresponding to the weak address to be refreshed, in the weak refresh operation.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.