Circuit arrangement and method with modified error syndrome for error detection of permanent errors in memories

US9646716B2 · kind B2 · utility

Assignee

• Infineon Technologies AG · DE

Inventors

• Michael Goessel · Roter Dudel, DE
• Sven Hosp · Potsdam, DE
• Guenther Niess · Potsdam, DE
• Klaus Oberlaender · San Jose, US

Key dates

• Filing date: Jul 31, 2014
• Grant date: May 9, 2017
• Expiry date: Aug 24, 2034

Classification

• Technology area (CPC G): Physics
• CPC primary: G11C2029/0411
• WIPO field: Computer technology
• WIPO sector: Electrical engineering

Abstract

A circuit arrangement for detecting memory errors is provided. The circuit arrangement comprises a memory (11) and an error detection circuit (12). The circuit arrangement is designed to store a code word of an error detection code (C) or a code word that is inverted in a subset (M) of bits in the memory (11) at a memory location and to read out a data word from the memory (11) from the memory location. The error detection circuit (12) is designed, for the case where a control signal present assumes a first value, to indicate a memory error if the data word is not a code word of the error detection code (C). Furthermore, the error detection circuit (12) is designed, for the case where the control signal present assumes a second value, which is different from the first value, and the code word that is inverted in the subset (M) of bits was written to the memory location, to determine on the basis of the data word read out from the memory (11) whether a memory error is present if the code word that is inverted in the subset (M) of bits is not a code word of the error detection code (C).