Hybrid subtractive etch/metal fill process for fabricating interconnects
US9646881B2 · kind B2 · utility
3Cited by
11References
20Claims
0Family size
Assignee
Inventors
Key dates
| Filing date | May 18, 2016 |
| Grant date | May 9, 2017 |
| Priority date | — |
| Expiry date | May 18, 2036 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH01L2924/14
- WIPO fieldSemiconductors
- WIPO sectorElectrical engineering
Abstract
In one example, a method for fabricating an integrated circuit includes patterning a layer of a first conductive metal, via a subtractive etch process, to form a plurality of lines for connecting semiconductor devices on the integrated circuit. A large feature area is formed outside of the plurality of conductive lines via a metal fill process using a second conductive metal.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.