Integrated circuit with backside structures to reduce substrate warp
US9646938B2 · kind B2 · utility
3Cited by
4References
20Claims
0Family size
Assignee
Inventors
Key dates
| Filing date | Oct 13, 2015 |
| Grant date | May 9, 2017 |
| Priority date | — |
| Expiry date | Oct 13, 2035 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH10D88/01
- WIPO fieldSemiconductors
- WIPO sectorElectrical engineering
Abstract
Wafer bowing induced by deep trench capacitors is ameliorated by structures formed on the reverse side of the wafer. The structures on the reverse side include tensile films. The films can be formed within trenches on the back side of the wafer, which enhances their effect. In some embodiments, the wafers are used to form 3D-IC devices. In some embodiments, the 3D-IC device includes a high voltage or high power circuit.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.