Integrated circuit packaging techniques and configurations for small form-factor or wearable devices

US9646953B2 · kind B2 · utility

Assignee

• Intel Corporation · US

Inventors

• Jackson Chung Peng Kong · Merang, MY
• Bok Eng Cheah · Air Itam, MY
• Kooi Chi Ooi · Air Itam, MY
• Shanggar Periaman · Butterworth, MY
• Michael P. Skinner · San Jose, US

Key dates

• Filing date: Nov 12, 2014
• Grant date: May 9, 2017
• Expiry date: Jan 14, 2035

Classification

• Technology area (CPC H): Electricity
• CPC primary: H01L2924/18161
• WIPO field: Semiconductors
• WIPO sector: Electrical engineering

Abstract

Embodiments of the present disclosure are directed toward integrated circuit (IC) packaging techniques and configurations for small form-factor or wearable devices. In one embodiment, an apparatus may include a substrate having a first side and a second side disposed opposite to the first side and a sidewall disposed between the first side and the second side, the sidewall defining a perimeter of the substrate, and a plurality of through-substrate vias (TSVs) disposed between the first side and the second side of the substrate, and a first dielectric layer disposed on the first side and including electrical routing features to route electrical signals of one or more dies in a plane of the first dielectric layer. Other embodiments may be described and/or claimed.